In an existing portable device, communication, video, audio, and multimedia applications are usually integrated into a single system in order to meet different user requirements. Accordingly, the design of the system gets very complicated. However, other factors of the system, such as the power consumption and battery lifespan, have to be taken into consideration at the same time when all user requirements are being satisfied. Thereby, system power consumption management has become an increasingly focused subject in the industry.
Dynamic voltage and frequency scaling (DVFS) is a very typical power consumption management technique, wherein the power consumption of a system is reduced by dynamically scaling the voltage and frequency (so that the system meets the lowest performance requirement) according to the requirements of different applications. FIG. 1 is a diagram of a conventional DVFS system. Referring to FIG. 1, the conventional DVFS system 100 includes a DVFS control unit 110, a clock generation unit 120, a power conversion unit 130, and a processor 140.
The DVFS system 100 determines a plurality of operating points before it starts its operation. Each operating point includes an operation frequency and a corresponding lowest voltage. The DVFS control unit 110 controls the power conversion unit 130 to convert an input voltage VIN into an operation voltage VDD, in turn outputing the operation voltage VDD to the processor 140 according to a selected operating point. Meanwhile, the DVFS control unit 110 controls the clock generation unit 120 to generate a clock signal CLK and outputs the clock signal CLK to the processor 140 according to the operating point.
When the DVFS system 100 is in operation, it works with one operating point. However, if the performance of the DVFS system 100 is to be increased, the DVFS control unit 110 first controls the power conversion unit 130 to increase its output voltage VDD, and then controls the clock generation unit 120 to increase the frequency of the clock signal CLK according to the predetermined operating point. On the contrary, if the performance of the DVFS system 100 is to be decreased, the DVFS control unit 110 reduces the frequency of the clock signal CLK before it reduces the operation voltage VDD. Accordingly, different frequencies and voltages are used with respect to different execution processes in an application thus reducing the power consumption.
However, some other overheads have to be taken into consideration when the DVFS system 100 is adopted, which will be further explained below.
Regarding the scaling of frequency, the clock generation unit 120 adopts a phase-locked loop (PLL) structure, requiring hundreds of reference clock cycles to complete one scaling operation. The latency of the hundreds of reference clock cycles results in a greater overhead on the performance of the DVFS system 100. Also, a shortest time limitation exists between two consecutive frequency scaling since the DVFS system 100 cannot work again before a frequency scaling operation is completed. In addition, by scaling the frequency of the DVFS system 100 with a PLL structure, it still has many limitations on working frequency and is insufficient to applications having different performance requirements. For example, in the reference article of “An all-digital clock generator for dynamic frequency scaling” published by W. H. Lin, C. C. Chen, and S. I. Liu in Proc. VLSI-DAT in April 2009, the scaling time is shortened by adopting a frequency divider along with the PLL structure. However, in such a structure, the frequency divisor has to be a power of 2. Thus, a DVFS system adopting such a structure can only provide a specific frequency setting due to the limitation in the frequency division, and such a specific frequency setting cannot satisfy the lowest performance requirements of different applications.
Presently, the scaling of voltage is usually accomplished by using an external DC-to-DC converter or a power management integrated circuit (PMIC), and herein the PMIC is controlled by using an inter-integrated circuit (I2C) control interface. A long conversion latency may be expected in the scaling of voltage.
As described above, even though the DVFS technique can improve the power consumption of a system, the corresponding overheads have to be evaluated and considered carefully when an application is designed based on the DVFS technique. For example, it takes about 200 microseconds (μs) to scale the frequency, about 200 μs to control an external PMIC through an I2C control interface, and about 750 μs to scale the voltage. All these time consumptions may affect the performance and power of the entire circuit design.